Method and apparatus for efficient matrix multiplication in a direct sequence CDMA system

ABSTRACT

A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of the input matrix to form groups of matrix elements. All possible permutations of partial results for each of the groups of matrix elements are pre-computed. The partial results from each of the groups of matrix elements are assigned to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results. The assigned partial results are summed along the first dimension of the matrix of assigned partial results to form a vector of full matrix multiplication results.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application also makes reference to, claims priority to and claims the benefit of U.S. provisional patent application Ser. No. 60/422,055 filed on Oct. 29, 2002.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate generally to a system and method for performing matrix multiplication, and more particularly to multiplying a vector by a matrix in a direct-sequence CDMA system.

A direct-sequence CDMA system is one form of a spread spectrum system for transmitting and receiving information. In a spread spectrum system, a transmitted signal is effectively spread over a wide band of frequencies. The wide band of frequencies is typically much wider than a minimum bandwidth of frequencies needed to transmit the information. The advantages of spreading a signal to be transmitted over a wide band of frequencies include interference rejection, secure communications, and code division multiplexing (using code sequences as information channels within a common radio channel, i.e. CDMA). CDMA allows the same band of frequencies to be shared with many users.

The direct-sequence method is a well-known and widely used spread spectrum technique that is easily implemented. In the direct-sequence method, a relatively narrow band transmit signal is modulated by a code sequence to create a wide band signal. Typically, the code sequence comprises a pseudo-random code having a fixed length. The rate of the code sequence is the chip rate where a chip corresponds to an element in the code sequence. The amount of spreading achieved is determined by the number of chips per transmit symbol in the original transmit signal.

When a transmitted spread spectrum signal is received, the signal must be de-spread to recover the original information. The method of de-spreading a signal is classified as a correlation process. De-spreading is typically accomplished by multiplying the spread spectrum signal with a copy of the code upon reception. As a result, the original transmitted signal may be recovered.

Different receivers may be accessed or addressed separately by designating a different code to each receiver. Codes may also be selected that have low cross correlation properties to reduce the potential for interference between receivers.

Often, the signals to be transmitted are digital signals that are represented as vectors of information symbols. Each symbol in a vector may correspond to a different information channel to be transmitted. A vector of information symbols may be coded or spread by multiplying the vector by a matrix of direct-sequence codes (one code per symbol in the vector) to form a spread spectrum vector to be transmitted.

Upon reception, the spread spectrum vector is de-spread by multiplying the spread spectrum vector by the inverse of the matrix of direct-sequence codes, therefore recovering the original vector of information symbols.

The matrix multiplication operations, if performed by brute force, require many multiplication and addition/subtraction operations, especially if the matrix of direct-sequence codes is of any significant size such as, for example, 128 elements by 128 elements. Matrix multiplication is often performed by, at least in part, a number of accumulators that accumulate the multiplied results for each code as the chip data becomes available. Assuming there are N different codes and Q chips per spread symbol in total, then a brute force implementation requires N×Q additions/subtractions for both spreading and de-spreading. Each operation translates into additional cost, hardware, and power consumption in the CDMA system.

It is desirable to greatly reduce the number of operations that are performed during the matrix multiplication process of the spreading and de-spreading functions in order to reduce cost, hardware, and power consumption in a direct-sequence CDMA system.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the present invention provide a system and method for performing efficient matrix multiplication in a direct-sequence CDMA system to facilitate the spreading and de-spreading of a sequence of information symbols.

A method of the present invention provides for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of the input matrix to form groups of matrix elements. All possible permutations of partial results for each of the groups of matrix elements are pre-computed. The partial results from each of the groups of matrix elements are assigned to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results. The assigned partial results are summed along the first dimension of the matrix of assigned partial results to form a vector of full matrix multiplication results.

Apparatus of the present invention provides, in a direct-sequence CDMA system, a pre-computation module to generate a matrix of partial results from an input matrix and an input vector by, in part, grouping elements of the input matrix across a second dimension of said input matrix. A post-computation module is also provided to sum along a first dimension of the matrix of partial results in a time-shared manner to form a vector of full matrix multiplication results as partial results in the matrix of partial results become available from the pre-computation module. The pre-computation module and post-computation module share a time-shared accumulator module to accumulate results.

Certain embodiments of the present invention afford an approach for efficiently multiplying a vector of uncoded or coded symbols by a matrix of direct-sequence codes or an inverse matrix of direct-sequence codes in a CDMA system where the elements of the matrix and inverse matrix comprise a limited number of possible values.

These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of an apparatus for performing efficient multiplication of a vector by a matrix in a direct-sequence CDMA system in accordance with an embodiment of the present invention.

FIG. 2 is a flowchart of a method for performing efficient multiplication of a vector by a matrix using the direct-sequence CDMA system of FIG. 1 in accordance with an embodiment of the present invention.

FIG. 3 is an exemplary illustration of a mathematical approach for multiplying a vector of uncoded symbols by a matrix of direct-sequence codes in a transmitter of a CDMA system in accordance with an embodiment of the present invention.

FIG. 4 is an exemplary illustration of a mathematical approach for multiplying a vector of coded symbols by an inverse matrix of direct-sequence codes in a receiver of a CDMA system in accordance with an embodiment of the present invention.

FIG. 5 is an exemplary illustration of grouping elements of a matrix to generate partial matrix multiplication results using a reduced number of adds/subtracts in accordance with an embodiment of the present invention.

FIG. 6 is an exemplary illustration of sixteen partial results P1 to P16 generated using the grouping of FIG. 5 in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of an architecture 5 for performing efficient multiplication of a vector by a matrix in a direct-sequence CDMA system in accordance with an embodiment of the present invention. The architecture 5 supports both spreading and de-spreading functions. The architecture 5 comprises a pre-computation module 10, a time-shared accumulator module 15, a post-computation module 20 and a full vector result register 30 in accordance with an embodiment of the present invention. The architecture 5 further comprises an analog-to-digital converter 40 and an ingress/channel cancellation filter 50.

In an embodiment of the present invention, uncoded analog symbols (or coded analog symbols) are input to an A/D converter 40, are digitized, and configured as an input vector. As an option, the vector of digital symbols may be filtered by ICF filter 50. The vector of digital symbols are fed into pre-computation module 10 along with a matrix of direct-sequence codes, M (or an inverse matrix of direct-sequence codes, M⁻¹), a grouping number G, and a number of adds/subtracts A used to perform pre-computation.

Referring to the method of FIG. 2, in an embodiment of the present invention, the pre-computation module 10 groups columns of the matrix M (or inverse matrix M⁻¹) according to the grouping number G in step 110. In step 120, all possible permutations of partial results for each grouping are pre-computed by pre-computation module 10 using time-shared accumulator module 15, performing only the number of adds/subtracts specified by A. In step 130, the partial results for each grouping are assigned to (correlated to) the appropriate rows of the matrix M (or inverse matrix M⁻¹) to form a matrix of assigned partial results. In step 140, columns of the matrix of assigned partial results are summed by post-computation module 20 using time-shared accumulator module 15 to form a vector of full matrix multiplication results that is stored in full vector register 30.

The details of one embodiment of a method are now discussed. In an embodiment of the present invention, the matrix of direct-sequence codes, M (or inverse matrix of direct-sequence codes, M⁻¹) comprises elements having values of only +1 or −1. Referring to FIG. 3, an input vector of 128 uncoded symbols [S₁ . . . S₁₂₈], to be transmitted by a CDMA transmitter, is input to pre-computation module 10. The input vector [S₁ . . . S₁₂₈] is to be effectively multiplied by matrix M which is a 128×128 element matrix comprising 128 direct-sequence codes of 128 chips each (i.e. each row in matrix M comprises a direct-sequence code of 128 chips or elements) in accordance with an embodiment of the present invention.

As may be seen in FIG. 3, when the vector [S₁ . . . S₁₂₈] is multiplied by the matrix M, the result is a vector of coded symbols [C₁ . . . C₁₂₈]. The coded symbols encompass a much larger signal bandwidth than the original uncoded symbols [S₁ . . . S₁₂₈]. The coded symbols [C₁ . . . C₁₂₈] may be transmitted to a CDMA receiver at a remote location.

A brute force computation of the matrix multiplication of [S₁ . . . S₁₂₈] by M would require 128×128=16,384 multiplies and 128×128=16,384 adds/subtracts for a total of 32,768 operations. However, since the matrix M comprises elements of only +1 or −1 in accordance with an embodiment of the present invention, the number of operations may be greatly reduced. As a result, the result of any coded symbol C_(j) comprises only the addition or subtraction of the original uncoded symbols [S₁ . . . S₁₂₈] as may be seen in FIG. 3. Each C_(j) comprises a unique combination of additions and subtractions according to the direct-sequence code in each row of matrix M.

Similarly, upon reception of the vector of coded symbols [C₁ . . . C₁₂₈], de-spreading may be accomplished by multiplying the vector of coded symbols [C₁ . . . C₁₂₈] by the inverse matrix M⁻¹ to recover the original vector of uncoded symbols [S₁ . . . S₁₂₈] as shown in FIG. 4. Since M is a matrix of +1's and −1's, M⁻¹ is also a 128×128 matrix comprising +1's and −1's. Therefore, each S_(j) comprises a unique combination of additions and subtractions of the coded symbols [C₁ . . . C₁₂₈] according to each row of matrix M⁻¹.

The method of FIG. 2 and the architecture of FIG. 1 allow the number of additions/subtractions to be greatly reduced according to an embodiment of the present invention. Specifically, referring to FIG. 5, assume the number of groupings, G, to be made in step 110 by pre-computation module 10 is four. Every four elements across rows of M⁻¹ are grouped together. Based on the grouping of four, there are only 2⁴=16 possible permutations of results for each grouping. For each grouping, only a total of 12 adds/subtracts are performed.

FIG. 5 shows a grouping of four upon reception of the coded symbols [C₁ . . . C₁₂₈]. The first grouping of four comprises [C₁ . . . C₄], the second grouping comprises [C₅ . . . . C₉], and so on across the entire inverse matrix M⁻¹. For the first grouping [C₁ . . . C₄], for example, sixteen combinations of [C₁ . . . C₄] are generated and then assigned (correlated) to the various rows of the inverse matrix M⁻¹, according to the 1's and −1's of each row, to form a first column of a matrix of partial results. The sixteen combinations (partial results P1 to P16) are assigned down all 128 rows of inverse matrix M⁻¹ and, therefore, are not unique to a row. In one embodiment, the redundancy due to the grouping is what reduces the number of required operations.

FIG. 5 illustrates that 12 adds/subtracts are used to generate the permutations of [C₁ . . . C₄]. First, 4 adds/subtracts are performed by pre-computation module 10 to generate a primary set of partial results. Then 8 more adds/subtracts are performed by pre-computation module 10 on the primary set of partial results to generate a set of 8 critical partial results.

FIG. 6 illustrates that, to obtain the sixteen partial results P1 to P16, from the 8 critical partial results, the sign of the 8 critical partial results is simply changed to obtain the other 8 permutations. Therefore, for any grouping of G=4, only A=12 adds/subtracts are performed during pre-computation. Again, the grouping and pre-computation of partial results is done across the entire inverse matrix M⁻¹ to effectively form a matrix of partial results. When the columns of the matrix of partial results are summed by post-computation module 20, the result is the original unspread vector [S₁ . . . S₁₂₈] which is stored in full vector result register 30.

If the grouping was not performed but, instead, the brute force method of performing every add/subtract in every row was used, the required number of adds/subtracts for the first 4 columns of the inverse matrix M⁻¹ would be much larger than 12.

In an embodiment of the present invention, the pre-computation module 10 processes the chips or columns of the inverse matrix M⁻¹ in a pipelined manner (i.e. each column or chip of the inverse matrix M⁻¹ is clocked through in succession). By waiting for the system to clock through, for example, 4 chips, the structure of the matrix and redundancy in the data may be taken advantage of to reduce the number of operations to be performed.

As a result, there are 12 adds/subtracts (pre-computations) per 4-chip time interval (grouping of 4 columns) plus an additional 128 adds per 4-chip time interval to sum down the resulting column of the matrix of partial results for the first 4 columns of the inverse matrix M⁻¹. This equates to 140 adds/subtracts per 4-chip time interval or 35 adds/subtracts per 1-chip time interval.

The brute force method of computing the results requires 128 adds/subtracts per 1-chip time interval. Therefore, instead of requiring 128 accumulators to perform 128 add/subtracts every 1-chip time interval, 35 accumulators may be used to perform 35 add/subtracts every 1-chip time interval in accordance with an embodiment of the present invention. The reduced number of 35 accumulators may be time-shared such that all computations are performed in the same amount of time as the brute force method of using 128 accumulators. The factor of savings in power and accumulator hardware is 128/35=3.657 (almost a factor of 4 savings).

In an embodiment of the present invention, time-shared accumulator module 15 comprises the 35 accumulators that are shared between pre-computation module 10 and post-computation module 20.

In other embodiments of the present invention, other groupings may be accomplished. The general formula for the factor of savings in power and accumulators for a 128×128 matrix M (or inverse matrix M⁻¹) is: 128/[A/G+ceiling(128/G)]  eqn. 1 where G is the number of chips that are grouped together, A is the number of adds/subtracts required for pre-computation, and ceiling is the round/up function.

The following table shows A for various groupings G.

G A 2 2 3 6 4 12 5 24 6 44 7 82 8 152

As may be seen, A is an exponential function of G because the number of permutations grows exponentially. As a result of the exponential growth, the linear factor of reduction by G is soon overcome by the growth of A. For the particular example of N=128 codes and Q=128 chips per code, the optimal G is 6 and yields a factor of 4.34 reduction in accumulators (adders) and power.

Also, it generally does not make sense to perform pre-computations beyond the inherent redundancy offered within the grouping window for 128 unique codes. For example, in a grouping window of 8, there are potentially 2⁸=256 possible results already, while there are only N=128 unique codes.

Even though the number of accumulators (adders) is reduced by grouping, pipeline registers are also used in the grouping process. Memory storage for 2^((G−1)) permutations of possible results are typically used. Therefore, for G=4, 35 accumulators (adders) are time-shared per 1-chip time interval, however, 2³=8 pipeline registers are typically used as well. As G increases, the number of pipeline registers increases and, therefore, the impact of using larger G should be carefully evaluated.

Other embodiments of the present invention are not limited to M or M⁻¹ having element values of +1 and −1. For example, an alternative embodiment of the present invention may limit element values to +2, +1, −1, and −2. Also, other embodiments of the present invention are not limited to vectors of length 128 or M or M−1 of dimensions 128×128. Other N-length vectors and N×Q matrices may be implemented in various embodiments of the present invention.

The various elements of the system and method may be combined or separated according to various embodiments of the present invention. For example, pre-computation module 10 and post-computation module 20 may be combined into a single processing module in accordance with an embodiment of the present invention.

In summary, certain embodiments of the present invention afford an approach to achieve significant reductions in power consumption, cost, and hardware by processing groups of chips in a direct-sequence CDMA system. For N unique codes and Q chips per code, the larger N is, and the smaller the set of base elements of matrix M, the better are the gains in efficiency. Q does not have much effect on the grouping process except that Q affects the rounding in the ceiling function.

While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims. 

1. In a direct-sequence CDMA system, apparatus having a processor to efficiently perform matrix multiplication, said apparatus comprising: a pre-computation module that generates a matrix of partial results from an input matrix and an input vector by, in part, grouping elements along a second dimension of said input matrix; and a post-computation module that sums along a first dimension of said matrix of partial results in a time-shared manner to form a vector of full matrix multiplication results as partial results in said matrix of partial results become available from said pre-computation module, wherein said vector of full matrix multiplication results comprises coded information for transmission over a wireless medium to one or more receivers.
 2. The apparatus of claim 1, comprising a time-shared accumulator module, shared between said pre-computation module and said post-computation module, that accumulates said partial results and said full matrix multiplication results.
 3. The apparatus of claim 1, comprising an analog-to-digital converter that digitizes said input vector before use by said pre-computation module.
 4. The apparatus of claim 1, comprising an ingress/channel cancellation filter that filters said input vector before use by said pre-computation module.
 5. The apparatus of claim 1, comprising a vector register that stores said vector of full matrix multiplication results.
 6. The apparatus of claim 1, wherein said input matrix comprises a matrix of direct-sequence codes.
 7. The apparatus of claim 1, wherein said input matrix comprises an inverse matrix of direct-sequence codes.
 8. The apparatus of claim 1, wherein said input vector comprises a vector of uncoded symbols.
 9. The apparatus of claim 1, wherein said input vector comprises a vector of coded symbols.
 10. The apparatus of claim 1, wherein each element of said input matrix comprises a value of +1 or −1.
 11. The apparatus of claim 1, wherein said grouping elements comprises performing an optimal grouping based on tradeoffs between performance, power, cost, and hardware for said CDMA system.
 12. The apparatus of claim 1, wherein said first dimension corresponds to a row dimension of said input matrix and said matrix of partial results.
 13. The apparatus of claim 1, wherein said second dimension corresponds to a column dimension of said input matrix and said matrix of partial results.
 14. A method for matrix multiplication within a direct-sequence CDMA system, the method comprising: generating, using a pre-computation module within the CDMA system, a matrix of partial results from an input matrix and an input vector by, in part, grouping elements along a second dimension of said input matrix, wherein said input vector comprises symbols to be coded for transmission over a wireless medium; and summing, using a post-computation module within the CDMA system, along a first dimension of said matrix of partial results in a time-shared manner to form a vector of full matrix multiplication results as partial results in said matrix of partial results become available from said pre-computation module, wherein said vector of full matrix multiplication results comprises coded information for transmission over said wireless medium to one or more receivers.
 15. The method of claim 14, comprising accumulating said partial results and said full matrix multiplication results using a time-shared accumulator module shared between said pre-computation module and said post-computation module.
 16. The method of claim 14, comprising digitizing, using an analog-to-digital converter, said input vector before use by said pre-computation module.
 17. The method of claim 14, comprising filtering, using an ingress/channel cancellation filter, said input vector before use by said pre-computation module.
 18. The method of claim 14, comprising storing, using a vector register, said vector of full matrix multiplication results.
 19. The method of claim 14, wherein said input matrix comprises a matrix of direct-sequence codes.
 20. The method of claim 14, wherein said input matrix comprises an inverse matrix of direct-sequence codes.
 21. The method of claim 14, wherein said input vector comprises a vector of uncoded symbols.
 22. The method of claim 14, wherein said input vector comprises a vector of coded symbols.
 23. The method of claim 14, wherein each element of said input matrix comprises a value of +1 or −1.
 24. The method of claim 14, wherein said grouping elements comprises performing an optimal grouping based on tradeoffs between performance, power, cost, and hardware for said CDMA system.
 25. The method of claim 14, wherein said first dimension corresponds to a row dimension of said input matrix and said matrix of partial results.
 26. The method of claim 14, wherein said second dimension corresponds to a column dimension of said input matrix and said matrix of partial results.
 27. A machine-readable storage having stored thereon, a computer program having at least one code section for matrix multiplication within a direct-sequence CDMA system, the at least one code section being executable by a machine for causing the machine to perform steps comprising: generating, using a pre-computation module within the CDMA system, a matrix of partial results from an input matrix and an input vector by, in part, grouping elements along a second dimension of said input matrix, wherein said input vector comprises symbols to be coded for transmission over a wireless medium; and summing, using a post-computation module within the CDMA system, along a first dimension of said matrix of partial results in a time-shared manner to form a vector of full matrix multiplication results as partial results in said matrix of partial results become available from said pre-computation module, wherein said vector of full matrix multiplication results comprises coded information for transmission over said wireless medium to one or more receivers.
 28. The machine-readable storage of claim 27, wherein said at least one code section comprises code for accumulating said partial results and said full matrix multiplication results using a time-shared accumulator module shared between said pre-computation module and said post-computation module.
 29. The machine-readable storage of claim 27, wherein said at least one code section comprises code for digitizing, using an analog-to-digital converter, said input vector before use by said pre-computation module.
 30. The machine-readable storage of claim 27, wherein said at least one code section comprises code for filtering, using an ingress/channel cancellation filter, said input vector before use by said pre-computation module.
 31. The machine-readable storage of claim 27, wherein said at least one code section comprises code for storing, using a vector register, said vector of full matrix multiplication results.
 32. The machine-readable storage of claim 27, wherein said input matrix comprises a matrix of direct-sequence codes.
 33. The machine-readable storage of claim 27, wherein said input matrix comprises an inverse matrix of direct-sequence codes.
 34. The machine-readable storage of claim 27, wherein said input vector comprises a vector of uncoded symbols.
 35. The machine-readable storage of claim 27, wherein said input vector comprises a vector of coded symbols.
 36. The machine-readable storage of claim 27, wherein each element of said input matrix comprises a value of +1 or −1.
 37. The machine-readable storage of claim 27, wherein said grouping elements comprises performing an optimal grouping based on tradeoffs between performance, power, cost, and hardware for said CDMA system.
 38. The machine-readable storage of claim 27, wherein said first dimension corresponds to a row dimension of said input matrix and said matrix of partial results.
 39. The machine-readable storage of claim 27, wherein said second dimension corresponds to a column dimension of said input matrix and said matrix of partial results.
 40. In a direct-sequence CDMA system, apparatus having a processor to efficiently perform matrix multiplication, said apparatus comprising: at least one module that generates a matrix of partial results from an input matrix and an input vector by, in part, grouping elements along a second dimension of said input matrix; and said at least one module sums along a first dimension of said matrix of partial results in a time-shared manner to form a vector of full matrix multiplication results as partial results in said matrix of partial results become available from said at least one module, wherein said vector of full matrix multiplication results comprises coded information for transmission over a wireless medium to one or more receivers.
 41. The apparatus of claim 40, wherein said at least one module comprises a first module that performs said generating of said matrix, and a second module that performs said summing.
 42. The apparatus of claim 41, wherein said first module comprises a pre-computation module and said second module comprises a post-computation module.
 43. The apparatus of claim 41, comprising a time-shared accumulator module, shared between said first module and said second module, that accumulates said partial results and said full matrix multiplication results.
 44. The apparatus of claim 40, comprising an analog-to-digital converter that digitizes said input vector before use by said at least one module.
 45. The apparatus of claim 40, comprising an ingress/channel cancellation filter that filters said input vector before use by said at least one module.
 46. The apparatus of claim 40, comprising a vector register that stores said vector of full matrix multiplication results.
 47. The apparatus of claim 40, wherein said input matrix comprises a matrix of direct-sequence codes.
 48. The apparatus of claim 40, wherein said input matrix comprises an inverse matrix of direct-sequence codes.
 49. The apparatus of claim 40, wherein said input vector comprises a vector of uncoded symbols.
 50. The apparatus of claim 40, wherein said input vector comprises a vector of coded symbols.
 51. The apparatus of claim 40, wherein each element of said input matrix comprises a value of +1 or −1.
 52. The apparatus of claim 40, wherein said grouping elements comprises performing an optimal grouping based on tradeoffs between performance, power, cost, and hardware for said CDMA system.
 53. The apparatus of claim 40, wherein said first dimension corresponds to a row dimension of said input matrix and said matrix of partial results.
 54. The apparatus of claim 40, wherein said second dimension corresponds to a column dimension of said input matrix and said matrix of partial results. 